1. Field of the Invention
This invention relates to the field of memory circuitry. More particularly, this invention relates to the reading of bit line voltages during memory read operations.
2. Description of the Prior Art
It is known to provide memories comprising an array of bit cells having bit lines running therethrough. The bit lines are precharged to a precharge voltage and then selectively discharged in dependence upon data values being read from the memory. The discharge of the voltages on the bit lines is sensed with sense amplifier circuitry which latches the data values to the output.
A problem within such memory circuits is that as device size has become smaller it is more difficult to match the devices within the sense amplifier circuit resulting in offsets and other mismatches which degrade the performance of the sense amplifier circuitry. In order to deal with this memory designers typically heavy margin the time required for a sense amplifier to read and latch a bit line voltage. Such heavy margining restricts the performance of the memory. In particular, a longer read time may be required in order that a change in bit line voltage due to the selective discharge becomes large enough to overcome any mismatch within the sense amplifier circuitry and accordingly be properly detected and latched.